1. Field of the Invention
The present invention relates to a semiconductor device and a method for making the semiconductor device, and more particularly to a buried contact hole structure.
2. Description of the Related Art
Recently, the design rule of highly integrated semiconductor memory devices has been reduced from about 1 xcexcm, i.e., the level of mega-bit grade DRAMs, to about 0.15 xcexcm, i.e., the level of giga-bit grade DRAMs. Due to such a reduction in a design rule, the size of a contact hole, which forms an electrical contact with a silicon substrate, has also been reduced. Because such a reduction in design rule in a vertical direction has been implemented using a three-dimensional capacitor structure, an aspect ratio has also been increased. However, the reduction in the diameter of the contact hole and the increased aspect ratio burdens a subsequent photolithography process. The design rule is one of the factors associated with so-called process limitations. In particular, the alignment tolerance in the deep submicron design rule is an important factor for determining a fatal failure of devices.
Development efforts associated with DRAM techniques have focused on an increase in capacitance within a limited unit area. As a result, capacitor structures have been developed from a planar cell structure to a stacked or trenched structure. Also, the stacked capacitor structure has been further developed to provide an increased effective capacitor area, e.g., using a cylinder or fin type capacitor structure.
Similar capacitor structure developments have been made in terms of the process sequence. That is, capacitor structures have been developed from a capacitor-under-bit-line (CUB) structure, in which capacitors are formed prior to the formation of bit lines, to a capacitor-over-bit-line (COB) structure, in which capacitors are formed after the formation of bit lines. In accordance with the COB structure, capacitors can be formed irrespective of the process margin given for a bit line process because the capacitors are formed after the formation of bit lines. Accordingly, the COB structure significantly increase capacitance within a limited cell area, as compared to the CUB structure. In other words, because the capacitors are formed over bit lines in the COB structure, storage node electrodes can have a maximum size determined by a limit given for the photolithography process, thereby providing a large capacitance.
However, such a COB structure increase the aspect ratio of a buried contact hole adapted to connect a storage node electrode to an active region of the device. Also, the misalignment margin between the storage node electrode and buried contact hole is reduced. In order to increase the misalignment margin between the storage node electrode and buried contact hole, it is necessary to reduce the buried contact hole to a minimum size, but it is also necessary to prevent the buried contact hole from being not-open, while increasing the storage node to a maximum size without causing the storage node to be bridged with neighboring storage nodes.
FIGS. 1 to 4 are cross-sectional views illustrating a conventional method for forming buried contacts in a semiconductor device.
Referring to FIG. 1, over a semiconductor substrate 10, a field oxide film 11 is formed using a well-known device isolation process, thereby defining, within the substrate 10, an active region and a field region. Thereafter, MOS transistors (not shown), each of which has a word line, and source and drain regions, are formed on the substrate 10.
Subsequently, an oxide film (not shown) is formed over the resulting structure obtained after the formation of the MOS transistors. The oxide film is then etched using a photoetching process, thereby forming contact holes (not shown) through which the source and drain regions of the MOS transistors are exposed. Over the resulting structure, a doped-polysilicon layer is deposited, and then the resulting structure is patterned to form landing pads 12 contacting respective source and drain regions. The landing pads 12 serve to reduce the aspect ratios of bit line contact holes and buried contact holes to be formed in a subsequent process.
A first interlayer insulating layer 13 is then formed over the resulting structure obtained after the formation of the landing pads 12. The first interlayer insulating layer 13 is etched using a photoetching process, thereby forming bit line contact holes (not shown) through which the landing pads 12 formed on the respective drain regions are exposed. Thereafter, a doped polysilicon layer 14, a tungsten silicide layer 15, and a capping layer (not shown) are sequentially formed over the resulting structure, and then patterned using a photoetching process, thereby forming bit lines 16 each having a polycide structure.
A second interlayer insulating layer 17 is formed over the resulting structure obtained after the formation of the bit lines 16. A high temperature oxide (HTO) film 18 is subsequently deposited over the second interlayer insulating layer 17. Using a photolithography process, a photoresist pattern 19 is then formed on the HTO film 18 in order to define buried contact hole regions. Thereafter, the HTO film 18, second interlayer insulating layer 17, and first interlayer insulating layer 13 are etched using the photoresist pattern 19 as a mask, thereby forming buried contact holes 20 through which the landing pads 12 formed on the respective source regions are exposed.
Referring to FIG. 2, removal of the photoresist pattern 19 is then carried out using an etching and stripping process. Thereafter, a nitride film is deposited over the resulting structure, and then etched back in accordance with a plasma dry etching process, thereby forming nitride spacers 22 on the side walls of the buried contact holes 20. In this case, an over-etching is conducted to completely open the bottom surface of each buried contact hole 20. During the etching process, the HTO film 18 is incidentally etched along with the nitride film at the top end of each buried contact hole 20 because of an insufficient etch selectivity between the nitride film and oxide film. As a result, the HTO film 18 has a slope or rounded corner at the top end of each buried contact hole 20, as shown in FIG. 2. Thus, each buried contact hole 20 has a flared opening at the top end thereof.
Referring to FIG. 3, a doped polysilicon layer 24 is then deposited over the resulting structure in such a manner that it completely fills the buried contact holes 20 a desired thickness.
Subsequently, a photoresist pattern 25 is formed on the polysilicon layer 24 using a photolithography process in order to define storage node regions, as shown in FIG. 4. Using the photoresist pattern 25 as a mask, the polysilicon layer 24 is then etched in accordance with a plasma dry etching process, thereby forming storage node electrodes 24a being connected to the landing pads 12 on the source regions via the buried contact holes 20.
The photoresist film pattern, which is to be used in the photoetching process for patterning the polysilicon layer for storage node electrodes, may often be misaligned from the buried contact holes. In such a case, however, the above mentioned conventional method involves problems because each buried contact hole has an inclined? top portion. That is, when the etching process is conducted at the inclined top portion of each buried contact hole, etching ions may scatter at that portion due to the above mentioned misalignment, thereby deflecting the etching direction. As a result, each storage node electrode may have a shape in which the polysilicon layer is partially recessed at a region corresponding to the top portion of the associated buried contact hole, as indicated by the reference numeral 26 in FIG. 4. This results in a reduction in the cross-sectional area of the storage polysilicon layer at the top end of each buried contact hole, thereby causing an increase in contact resistance. Furthermore, it is impossible to form a dielectric layer having a uniform thickness in a subsequent process. As a result, a leakage of cell capacitance and malfunction of the device may occur.
The above mentioned problems may be more severe when the misalignment margin between the storage node electrode and the buried contact hole is reduced by virtue of a reduction in design rule.
Therefore, an object of the invention is to provide a buried contact hole structure in a semiconductor device and a method for making the buried contact hole structure which are capable of providing a sufficient misalignment margin between a buried contact hole and a line arranged over the buried contact hole.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor substrate having a semiconductor element formed on an upper surface of the semiconductor substrate; a first interlayer insulating layer formed over the semiconductor substrate, the first interlayer insulating layer having a contact hole; a first line formed on the first interlayer insulating layer in such a fashion that it is connected to the semiconductor element via the contact hole; a second interlayer insulating layer over the first line and the first interlayer insulating layer; an etch barrier layer formed on the second interlayer insulating layer; a buried contract hole extending through both the etch barrier layer and the second interlayer insulating layer in such a fashion that the semiconductor element is exposed; an insulating spacer formed on an inner side wall of the buried contact hole; and a second line formed on the etch barrier layer in such a fashion that it is connected to the semiconductor element via the buried contact hole; and wherein the buried contact hole has a vertical profile at a top end thereof to provide a sufficient misalignment margin between the buried contact hole and the second line.
Preferably, the semiconductor device further comprises a pair of landing pads interposed between the semiconductor element and the first interlayer insulating layer and connected to the semiconductor element. The landing pads are spaced apart from each other by a desired distance extending in a direction parallel to the upper surface of the semiconductor substrate. In this case, the first line is connected to one of the landing pads, and the second line is connected to the other landing pad.
Preferably, the semiconductor device further comprises a cap insulating layer formed over the etch barrier layer and having a wet etch selectivity with respect to the etch barrier layer. In this case, the buried contact hole extends to the cap insulating layer.
The semiconductor device preferably further comprises a conductive plug formed in the buried contact hole. In this case, the second line is directly connected to the conductive plug.
Preferably, the semiconductor device is a DRAM cell. In this case, the first line is a bit line, and the second line is a storage node electrode of a capacitor.
In accordance with another aspect of the present invention, to fabricate a semiconductor device, a first interlayer insulating layer is deposited over a semiconductor substrate having a semiconductor element formed on an upper surface of the semiconductor substrate. A first line is formed on the first interlayer insulating layer in such a fashion that it is connected to the semiconductor element via a contact hole formed through the first interlayer insulating layer. Then, a second interlayer insulating layer is deposited over the resulting structure. Next, an etch barrier layer is formed on the second interlayer insulating layer. A cap insulating layer having a wet etch selectivity with respect to the second interlayer insulating layer is deposited over the etch barrier layer. Subsequently, the insulating layer, the etch barrier layer, and the second interlayer insulating layer are etched to form a buried contract hole to expose the semiconductor element. An insulating spacer is formed on an inner side wall of the buried contact hole. At least a portion of the cap insulating layer is etched. A conductive layer is deposited over the resulting structure. Then, the conductive layer is patterned to form a second line connected to the semiconductor element via the buried contact hole.
Preferably, the method further comprises the step of forming, prior to the deposition of the first interlayer insulating layer, a pair of spaced landing pads on the semiconductor substrate in such a fashion that they are connected to the semiconductor element.
In accordance with another aspect of the present invention, a method for making a semiconductor device comprises depositing a first interlayer insulating layer over a semiconductor substrate having a semiconductor element formed on an upper surface of the semiconductor substrate; forming a first line on the first interlayer insulating layer in such a fashion that it is connected to the semiconductor element via a contact hole formed through the first interlayer insulating layer; depositing a second interlayer insulating layer over the resulting structure; depositing an etch barrier layer on the second interlayer insulating layer; depositing, over the etch barrier layer, a cap insulating layer having a wet etch selectivity with respect to the etch barrier layer; etching the cap insulating layer, the etch barrier layer, and the second interlayer insulating layer, thereby forming a buried contract hole for exposing the semiconductor element; forming an insulating spacer on an inner side wall of the buried contact hole; depositing a first conductive layer over the resulting structure, and removing the first conductive layer until an upper surface of the insulating layer is exposed, thereby forming a plug in the buried contact hole; wet etching at least a portion of the cap insulating layer; and depositing a second conductive layer over the resulting structure; and patterning the second conductive layer, thereby forming a second line directly connected to the plug.
The first conductive layer is deposited to a thickness capable of sufficiently filling the buried contact hole.
In accordance with the present invention, buried contact holes are formed to have a vertical profile at respective top ends thereof. During a photoetching process for forming storage node electrodes, accordingly, there is no phenomenon that the material of those storage node electrodes is abnormally etched at respective top ends of associated buried contact holes, even when there is a misalignment between the photomask used in the photoetching process and the buried contact holes.